A digital/analog converter tends to produce a glitch due to a transient state of different on and off switching times of semiconductor switching means provided therein. Such glitch has to be prevented from occurring.
In one prior art reference, it has been conventionally employed that a sample holding circuit is provided at an output of the digital/analog converter to remove the glitch produced therein. However, it is difficult to control the timing and in addition thereto the construction of the circuit is disadvantageously complicated.
In another prior art, the digita/analog converter has been proposed to have means to prevent the glitch from being produced by itself. However, the commercially available digital/analog converter of such type which is formed as an integrated circuit as a practical matter still produces the glitch.
In a further prior art, the digital/analog converter has been proposed to have means to make consistent the rise and fall times of the digital input signal because the glitch is produced by the inconsistency of those times which are in turn produced due to digital signal output means supplying the digital signal to the digital/analog converter. However, this cannot effectively prevent the shifting of the timing of turning on and off the switching means in the digital/analog converter, which causes the glitch to be produced. Thus, this cannot prevent the glitch from being produced.
Finally, of late, a high speed latching circuit of complementary metal oxide semiconductor (CMOS) is commercially available which can supply the digital signal having the rise and fall times of the digital signal substantially equal to each other. Thus, it will be noted that there is not required a means to make consistent the rise and fall times of the digital signal with such high speed latching circuit. However, the glitch is also caused by either of such characteristics of one of the raising up and down times advanced more than the other because a plurality of switching means formed as a semiconductor circuit have the switching characteristic selected at each bit of the converter. Therefore, it will be noted that the glitch is produced due to such switching characteristic of the digital/analog converter. As described later in detail with reference to FIGS. 3A and 3B, the glitch can be prevented if a threshold voltage Vt can be adjusted to become V.sub.t1 or V.sub.t2, respectively, as indicated in FIGS. 3A and 3B. Since the switching characteristics of the switching means corresponding to the bits are not strictly consistent, the problem cannot be completely solved even though the threshold voltages are raised up or down in a uniform manner. Those commercially available digital/analog converters which are capable of adjustment are adapted to adjust the threshold voltages only in a uniform manner. Also, there is commercially available a digital/analog converter having no ability to adjust the threshold voltages. Thus, it will be noted that the glitch still cannot be prevented from occurring in case the commercially available digital/analog converter is provided in an electronic instrument.